Method of manufacturing a ferroelectric capacitor

ABSTRACT

In the manufacture of an integrated circuit memory capacitor, an underlying hydrogen barrier layer, either electrically nonconductive or conductive, is formed on a substrate. Then, the lower electrode layer and the ferroelectric/dielectric layer are formed and selectively etched. A nonconductive hydrogen barrier layer is formed on the dielectric layer and selectively etched. After a heat treatment in oxygen, the upper electrode layer and a conductive hydrogen barrier layer are successively deposited and selectively etched. The nonconductive hydrogen barrier layer covers the capacitor except for a part of the upper electrode, and the conductive hydrogen barrier layer covers a portion where there is no nonconductive hydrogen barrier layer. Thus, the underlying barrier layer, the nonconductive barrier layer and the conductive barrier layer together completely cover the memory capacitor. The dielectric layer comprises a ferroelectric or high-dielectric constant metal oxide. The nonconductive hydrogen barrier layer is typically SiN. The conductive hydrogen barrier layer is typically a metal nitride, such as TiN or AIN.

RELATED APPLICATIONS

This application is a divisional application of application Ser. No.09/197,919 filed Nov. 23, 1998, U.S. Pat. No. 6,180,971.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a capacitor and a method of manufacturing thesame, and in particular to a capacitor including a ferroelectricsubstance that is used for a semiconductor memory and a method ofmanufacturing the same.

2. Statement of the Problem

A ferroelectric memory which has a combination of a semiconductor and aferroelectric substance, such as Pb(Zr_(1−x)Ti_(x))O₃ (hereinafter“PZT”) stores “1” and “0” in memory by using residual polarization ofthe ferroelectric substance. The relation between a voltage applied tothe ferroelectric capacitor and the polarization is represented as ahysteresis characteristic in FIG. 16.

For example, even when a positive bias is applied and thereafter thebias is returned to zero, the polarization does not return to zero andis held at the residual polarization +Pr. Conversely, when the bias isput into negative and thereafter the bias is returned to zero, theresidual polarization −Pr is obtained. These states are read out andrecognized as “1” and “0”, which can be used as a memory by readingthem. It is known to operate as a nonvolatile memory because theinformation is retained even when a power source is cut off. It isimportant that the ferroelectric capacitor and a large-scale integratedcircuit (hereinafter “LSI”) are formed on the same substrate so thatboth operate with sufficient performance in this memory. Such astructure of a capacitor is disclosed in Japanese Unexamined PatentPublication No. Hei 7-111318/1995. FIG. 17 is a structuralcross-sectional view thereof. In FIG. 17, the reference numeral 21represents an underlying oxide film (BPSG) layer, the reference numeral23 represents a lower electrode (Pt) layer, the reference numeral 24denotes a PZT layer, the reference numeral 25 denotes a SiN layer, thereference numeral 26 represents an upper electrode (Pt) layer, thereference numeral 27 represents a TiN layer, the reference numeral 28denotes a capacitor cover (NSG) layer, and the reference numeral 29denotes an Al wiring layer.

In the capacitor having such a structure, the ferroelectric capacitorcomprising lower electrode layer 23, dielectric layer 24 and upperelectrode layer 26 is completely covered with SiN layer 25 and TiN layer27. Although the SiN layer 25 and the TiN layer 27 are unnecessary toobtain a ferroelectric capacitor which operates normally, the reason forforming them will be explained.

Namely, in the normal LSI process, a heat treatment is carried out in ahydrogen atmosphere at about 400° C. after formation of an Al wiring.This heat treatment is performed to reduce MOS interface levels whichare generated in each step of the MOSFET fabrication used for the LSIand to reduce the variation thereof; in particular, the variation ofthreshold values. It is necessary to perform the heat treatment in thehydrogen atmosphere after the formation of the capacitor to improve thecharacteristic of the MOSFET, which is formed in the same substrate.However, a reduction reaction takes place during such a process becausethe ferroelectric material, such as PZT, is generally an oxide.

Consequently, oxygen deficiency occurs in the ferroelectric substancedue to the heat treatment in the hydrogen. The oxygen deficiency bringsabout loss of ferroelectric characteristic and an increase of leakagecurrent. As a result, the capacitance after the heat treatment isinsufficient to serve in a ferroelectric capacitor.

Therefore, it is necessary in the ferroelectric capacitor to form acover film having a barrier characteristic against the hydrogen. Such afilm may be, for example, a SiN layer 25 or a TiN layer 27. With such astructure, the ferroelectric capacitor is completely covered with thesefilms and does not deteriorate as a result of the heat treatment in thehydrogen.

Problems of the capacitor having the above structure and a method ofmanufacturing the same are described here. With such a structure, it isnecessary to deposit SiN on the entire surface after the ferroelectriccapacitor has been formed. In consideration of density and the stepcoverage of the film, the deposition is carried out by use of a chemicalvapor deposition (hereinafter “CVD”) method.

Conventionally, the deterioration due to a variety of reductionprocesses after the formation of the capacitor has caused problems inthe ferroelectric capacitor used in a semiconductor memory. To solve theproblems, it is effective to form a cover film, such as SiN, having abarrier characteristic against the hydrogen. However, deterioration alsooccurs during the formation of the film because a gas containinghydrogen, such as SiH₄ (ammonia), is used during the deposition of theSiN. SiH₄ (silane) and NH₄ are generally used as gases for thedeposition of SiN. Furthermore, a deposition temperature of 300° C. ormore is required to obtain SiN having dense and excellent film quality.

Therefore, a reduction reaction occurs during the deposition due to thehydrogen contained in the gas, which results in deterioration of theferroelectric characteristic. Thus, although the barrier characteristicis effective against the hydrogen after the deposition, deteriorationtakes place during the deposition itself because the reduction reactionoccurs.

The above problem may be solved by using TiN that is deposited as thebarrier film by a sputtering method. In contrast to SiN, however, TiN iselectrically conductive, so it interferes with wiring material, such asan Al wiring pattern. Consequently, it is impossible to cover the entirecapacitor.

Therefore, although no deterioration occurs by heat treatment afterformation of the structure, deterioration takes place during themanufacturing process. Further, the fabrication process is excessivelycomplex.

3. Solution to the Problem

It is an object of this invention to provide a structure of a capacitorand a method of manufacturing the same, in which a cover film on thecapacitor has the barrier characteristic against hydrogen withoutcausing deterioration of ferroelectric and dielectric characteristics.

According to the invention, a memory device has capacitor with a lowerelectrode layer, a dielectric layer and an upper electrode layer. Anonconductive hydrogen barrier layer is located on the capacitor exceptfor a region on at least part of the upper electrode layer, while aconductive hydrogen barrier layer is formed at least partly in theregion in which the nonconductive hydrogen barrier layer is not located.

Further, according to a method of manufacturing the capacitor of thisinvention, the lower electrode layer and the dielectric layer aresuccessively deposited. After the lower electrode layer and thedielectric layer are selectively etched, the nonconductive hydrogenbarrier layer is deposited on the above structure. After thenonconductive hydrogen barrier layer is selectively etched on thedielectric layer, a heat treatment is carried out at a temperature of400° C. or more, preferably in oxygen. Thereafter, the upper electrodelayer and the conductive hydrogen barrier layer are successivelydeposited, followed by a selective etch of the upper electrode layer andthe conductive hydrogen barrier layer. In this embodiment, the upperelectrode layer and the conductive hydrogen barrier layer areself-aligning. The nonconductive hydrogen barrier layer and theconductive hydrogen barrier layer may be deposited using chemical vapordeposition.

According to an alternative embodiment of the method of manufacturing acapacitor of this invention, the lower electrode layer and thedielectric layer are successively deposited on a base substrate. Afterthe lower electrode layer and the dielectric layer are selectivelyetched, the nonconductive hydrogen barrier layer is deposited on theabove structure. After the nonconductive hydrogen barrier layer isselectively etched on the dielectric layer, a heat treatment is carriedout at a temperature of 400° C. or more, preferably in oxygen. Then, anelectrode layer is deposited and selectively etched to form the upperelectrode layer, and thereafter the conductive hydrogen barrier layer isdeposited and selectively etched. In this embodiment, the upperelectrode layer and the conductive hydrogen barrier layer are patternedseparately and are, therefore, not self-aligned with each other. Rather,the conductive hydrogen barrier layer covers more than just the upperelectrode.

In an embodiment of the invention, an underlying electricallynonconductive hydrogen barrier is located below the lower electrodelayer on the entire surface of the base substrate on which the capacitoris formed. In another embodiment of the invention, an underlyingconductive hydrogen barrier layer is located below the lower electrodelayer and is etched and PATTERNED together with the lower electrodelayer. The base substrate may be a silicon substrate. According to theinvention, a base insulating film may be located on the substrate. Theunderlying conductive hydrogen barrier layer or the underlyingnonconductive hydrogen barrier layer may be located directly on asubstrate or on an insulating film that is on the substrate. Anintegrated circuit may also be located on the substrate.

When the nonconductive hydrogen barrier layer is etched, an openingcorresponding to the upper electrode is formed. The heat treatment inoxygen, before deposition of the upper electrode layer and theconductive hydrogen barrier layer, serves to recover the deteriorationof properties of the dielectric layer caused by reduction reactions inprior manufacturing processes.

Furthermore, after deposition of the upper electrode layer and theconductive hydrogen barrier layer, the opening through the nonconductivehydrogen barrier is completely covered with the conductive hydrogenbarrier layer. Consequently, the above structure possesses a barriercharacteristic against the hydrogen process after formation of thecapacitor, resulting in no deterioration in the dielectric layer duringsubsequent reducing processes.

A feature of the invention is that the dielectric layer may contain aferroelectric material or a high dielectric-constant material. Theferroelectric material is a ferroelectric metal oxide, such asPb(Zr,Ti)O₃ and SrBi₂Ta₂O₉. The high dielectric-constant material is anonferroelectric dielectric metal oxide, such as (Sr,Ba)TiO₃.

The nonconductive hydrogen barrier layers may comprise SiN. It is afeature of the invention that a SiN film or other nonconductive hydrogenbarrier layer may be deposited using a chemical vapor deposition method.The conductive hydrogen barrier layers typically comprise a metalnitride. Such metal nitrides include TiN and AlN.

The conductive hydrogen barrier layer may be located directly on theupper electrode layer. Also, a buffer film may be located on the upperelectrode, with the conductive hydrogen barrier layer located on thebuffer film.

After the upper electrode and the conductive hydrogen barrier layer arepatterned into the predetermined shape, typically an insulatingcapacitor cover layer is deposited on the capacitor, a contact hole isformed by the etching, and an Al wiring pattern is formed. The capacitorcover layer may be formed using a chemical vapor deposition method.

Usually after the insulating film and wiring layer are formed, ahydrogen heat treatment may be conducted, typically at a temperature of300° C. or higher.

Therefore, the heat treatment in the hydrogen can be carried out toimprove the characteristic of the MOSFET. Consequently, a memory havingan excellent characteristic can be obtained with an excellent yield.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a first embodiment of acapacitor of this invention;

FIG. 2 is a cross-sectional view showing a second embodiment of acapacitor of this invention;

FIG. 3 is a cross-sectional view showing a third embodiment of acapacitor of this invention;

FIGS. 4-15 are a series of cross-sectional views showing successivesteps of a method of manufacturing the capacitor of the firstembodiment, shown in FIG. 1;

FIG. 16 is a characteristic diagram showing an example of hysteresischaracteristic between a voltage applied to the conventionalferroelectric capacitor and polarization obtained at that time;

FIG. 17 is a structural cross-sectional view showing an example of theconventional capacitor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

1. Overview

This description focuses principally on capacitors containingferroelectric oxide material, such as PZT and SrBi₂Ta₂O₉. But thestructure and method of the invention are also useful when a capacitorcontains nonferroelectric dielectric material, such as (Sr,Ba)TiO₃.Since all ferroelectric oxides are also dielectric materials, thegeneral term “dielectric” as used in this disclosure refers both toferroelectric oxides and to nonferroelectric dielectric oxides.

This description also focuses on the preferred embodiment, in which theconductive hydrogen barrier layers comprise TiN, and the nonconductivehydrogen barrier layers comprise SiN. But the structures and methods ofthe invention are useful with other compositions of material.

It should be understood that the FIGS. 1-15 depicting integrated circuitdevices in accordance with the invention are not meant to be actual planor cross-sectional views of any particular portion of an actualintegrated circuit device. In the actual devices, the layers will not beas regular and their thicknesses may have different proportions. Thevarious layers in actual devices often are curved and possessoverlapping edges. The figures instead show idealized representationswhich are employed to depict more clearly and fully the structures andmethods of the invention than would otherwise be possible. Also, thefigures represent only one of innumerable variations of ferroelectricdevices that could be fabricated using the method of the invention.

The terms of orientation herein, such as “above”, “upper” and “over”,and “below”, “lower” and “underlying”, relate to the silicon substrate102. For example, if a second element is “above” a first element, itmeans it is farther from the substrate 102; and if it is “below” anotherelement, then it is closer to the substrate 102 than the other element.The long dimension of substrate 102 defines a plane that is consideredto be a “horizontal” plane herein, and directions perpendicular to thisplane are considered to be “vertical”. To “cover” an object means overand extending the entire breadth and width of an object. None of theabove terms necessarily include the limitation of being in directcontact, though in some embodiments an element that is above, over,below, or underlying another element can also be in direct contact withthe other element.

For the sake of clarity, the same reference numbers have been used toidentify similar elements among the different embodiments of theinvention depicted in the figures.

2. Detailed Description

FIG. 1 is a cross-sectional view showing a capacitor according to afirst embodiment of this invention. In FIG. 1, the reference numeral 1represents a base insulating film (e.g., boron phospho-silicate glass,hereinafter “BPSG”); the reference numeral 2 represents an underlying,first conductive hydrogen barrier layer (e.g., TiN); the referencenumeral 3 denotes a lower electrode layer (e.g., Pt); the referencenumeral 4 denotes a dielectric layer (e.g., PZT); the reference numeral5 represents a nonconductive hydrogen barrier layer (e.g., SiN); thereference numeral 6 represents an upper electrode layer (e.g., Pt); thereference numeral 7 denotes a second conductive hydrogen barrier layer(e.g., TiN); the reference numeral 8 denotes a capacitor cover layer(e.g., NSG); and the reference numeral 9 represents a wiring layer(e.g., Al).

In such a structure of a capacitor according to the first embodimentillustrated in FIG. 1, a ferroelectric capacitor comprising a lowerelectrode layer 3, a dielectric layer 4, and an upper electrode layer 6,which are formed on the base insulating film 1, is completely enclosedwithin nonconductive hydrogen barrier layer 5 and the first and secondconductive hydrogen barrier layers 2 and 7. Consequently, nodeterioration of capacitor electronic properties occurs even when a heattreatment in hydrogen is conducted after formation of the capacitor.

The dielectric layer typically comprises a metal oxide material, such asPb(Zr_(1−X)Ti_(X))O₃, SrBi₂Ta₂O₉ (hereinafter “SBT”) and(Ba_(1−X)Sr_(X))TiO₃ 9 (hereinafter “BST”). The upper electrode layer 6and the lower electrode layer 3 typically include materials such as Pt,Ir, IrO₂, Ru and RuO₂.

An electrically conductive hydrogen barrier layer typically comprises ametal nitride, such as titanium nitride (hereinafter “TiN”) or aluminumnitride (hereinafter “AlN”). A nonconductive hydrogen barrier layertypically comprises a material such as silicon nitride (hereinafter“SiN”).

The capacitor is formed directly on a substrate, such as a siliconsubstrate, or on a base insulating film located between the substrateand the capacitor. An integrated circuit can be formed on the substrate.

The term “self-aligned” is used to refer to one or more layers formedand patterned in such a manner that they automatically align with one ormore other layers. For example, if upper electrode layer 6 and secondconductive hydrogen barrier layer 7 are patterned together in the samephotomask and etch patterning process, they will be self-aligned.

Although the conductive hydrogen barriers, such as TiN, are conductive,the first conductive hydrogen barrier layer 2 and second conductivehydrogen barrier layer 7 are integrated with and self-aligned with thelower and upper electrode layers 3 and 6, respectively. Consequently, inthe embodiment depicted in FIG. 1, the conductive hydrogen barriers donot electrically contact with the dielectric layer 4 of the capacitor.In the above structure, the lower portion of the capacitor is coveredwith the underlying, or first, conductive hydrogen barrier layer 2,while most of the side surface and the upper surface is covered with thenonconductive hydrogen barrier layer 5. The portion of the upper surfacehaving no nonconductive hydrogen barrier layer 5 is covered with thesecond conductive hydrogen barrier layer 7.

Therefore, the capacitor possesses a barrier against the hydrogen or thereduction atmosphere. Further, the second conductive hydrogen barrierlayer 7 may be formed directly or via a buffer layer (not shown) on theupper electrode layer 6.

FIG. 2 is a cross-sectional view showing a capacitor according to asecond embodiment of this invention. In the second embodiment, anunderlying, or first, nonconductive hydrogen barrier layer 15 is formedover the entire base insulating film 1, instead of a first conductivehydrogen barrier layer 2, as in the first embodiment. In thisembodiment, the lower portion of the capacitor is covered with the firstnonconductive hydrogen barrier layer 15 to obtain the same barriereffect as in the first embodiment.

FIG. 3 is a cross-sectional view showing a capacitor according to athird embodiment of this invention. In the third embodiment, the upperelectrode layer 6 is not self-aligned with the second conductivehydrogen barrier layer 7. Further, the second conductive hydrogenbarrier layer 7 in the third embodiment is larger in shape than thesecond conductive hydrogen barrier layer 7 in the first embodiment.

In the first and second embodiments, hydrogen that slightly invades fromthe side surface of the upper electrode layer 6 may react with theferroelectric or dielectric substance in a reduction reaction becausethe upper electrode layer 6 does not act as a barrier against hydrogen.In the structure of FIG. 3, on the other hand, the barrier effect isfurther improved in comparison with the first and second embodimentsbecause the side surface of the upper electrode layer 6 is also coveredwith the second conductive hydrogen barrier layer 7.

The fabrication of the capacitor according to the embodiment depicted inFIG. 1 is described with reference to FIGS. 4-15. An underlying, orfirst, conductive hydrogen barrier layer 2, a lower electrode layer 3,and a dielectric layer 4 are successively deposited on a substrate (notshown). After the first conductive hydrogen barrier layer 2, the lowerelectrode layer 3, and the dielectric layer 4 are selectively etched, anonconductive hydrogen barrier layer 5 is deposited on the abovestructure. After the nonconductive hydrogen barrier layer 5 isselectively etched on the dielectric layer 4, a heat treatment iscarried out at 400° C. or higher. The heat treatment is carried out inan oxygen atmosphere after the nonconductive hydrogen barrier layer 5 ispartially removed from the dielectric layer 4. Thereafter, an upperelectrode layer 6 and a second conductive hydrogen barrier layer 7 aresuccessively deposited and selectively etched to form the upperelectrode layer 6 and the second conductive hydrogen barrier layer 7.

After the upper electrode layer 6 and the second conductive hydrogenbarrier layer 7 are patterned, a capacitor cover layer (insulating film)8 is formed on the entire surface. Capacitor cover layer 8 is depositedpreferably by the use of a chemical vapor deposition (“CVD”) method.Further, after a wiring layer 9 is formed on the capacitor, a heattreatment is performed in a hydrogen atmosphere. The heat treatment inthe hydrogen atmosphere is conducted at a temperature of 300° C. orhigher.

In the structure illustrated in FIG. 2, an underlying, or first,nonconductive hydrogen barrier layer 15 is formed instead of a firstconductive hydrogen barrier layer 2. The nonconductive hydrogen barrierlayers 5 and 15 are deposited by use of a CVD method.

FIGS. 4-15 depict schematic cross-sectional views of successive steps inthe manufacture of a capacitor according to the first embodiment.

In the step depicted in FIG. 4, the underlying, or first, conductivehydrogen barrier layer 2, the lower electrode layer 3, and thedielectric layer 4 are successively deposited on the base insulatingfilm (not shown in FIG. 4). In the step depicted in FIG. 5, thedielectric layer 4, the lower electrode layer 3, and the firstconductive hydrogen barrier layer 2 are selectively etched to form apattern of the lower electrode. In the step depicted in FIG. 6, thedielectric layer 4 is selectively etched to form a pattern of thecapacitor. In the step depicted in FIG. 7, nonconductive hydrogenbarrier layer 5 is deposited on the entire surface. Thereafter, in thestep depicted in FIG. 8, portions of nonconductive hydrogen barrierlayer 5 are selectively etched down to dielectric layer 4 and lowerelectrode 3.

Next, the heat treatment is carried out in the oxygen atmosphere in thestep depicted in FIG. 9. Thus, the oxygen deficiency due to thereduction reaction during the deposition of nonconductive hydrogenbarrier layer 5 is compensated. In the step depicted in FIG. 10, upperelectrode layer 6 and second conductive hydrogen barrier layer 7 aresuccessively deposited on the entire surface, to be selectively etchedto the desired shape in the step depicted in FIG. 11. In such astructure, the second conductive hydrogen barrier layer 7 is located ina region from which the nonconductive hydrogen barrier layer 5 wasetched out.

Subsequently, capacitor cover layer 8 is deposited on the entire surfacein the step depicted in FIG. 12. In the step depicted in FIG. 13,capacitor cover film layer 8 is selectively etched to form contactholes. In the step depicted in FIG. 14, the wiring layer 9 is depositedon the entire surface, to be selectively etched in the step depicted inFIG. 15.

In a capacitor according to the invention, no deterioration is caused bythe hydrogen treatment after the formation of the capacitor. Inaddition, no problem results from deterioration due to reduction duringthe manufacturing steps.

In reference again to FIGS. 4-15, successive steps of the manufacture ofa capacitor with the structure in accordance with the first embodimentare described in detail.

In the preferred embodiment, the underlying, or first, conductivehydrogen barrier layer 2 of TiN, the lower electrode layer 3 of Pt, andthe dielectric layer 4 of PZT are successively deposited on the baseinsulating film 1 (BPSG) in the step depicted in FIG. 4. These layersmay be deposited by use of a sputtering method. However, the PZT may beformed by a sol-gel method. The TiN and Pt have suitable properties whenthey are deposited at room temperature. On the other hand, to possessgood ferroelectric properties, it is necessary that the PZT have goodcrystallinity. To this end, a crystallization temperature of about 600°C. is required. Other crystalline ferroelectric and dielectric materialsalso require similarly high heat-treatment temperatures in oxygen.

Further, TiN may be deposited by a CVD method. The film thickness of TiNis about 100 nm while the film thickness of Pt and dielectric is about200 nm. In the structure according to the second embodiment, anunderlying nonconductive hydrogen barrier layer 15 of SiN with about 50nm thickness is deposited, instead of an underlying, or first,conductive hydrogen barrier layer 2. In this case, a deposition methodfor obtaining good film quality, such as a CVD method, is desirable.

Subsequently, in the step depicted in FIG. 5, the dielectric layer 4,the lower electrode layer 3, and the first, underlying conductivehydrogen barrier layer 2 are selectively etched to form a pattern of thelower electrode layer 3. This process is carried out by the use ofreactive ion etching (hereinafter “RIE”) using a photoresist as a mask.Although a chlorine-based gas is used in this case, an excellent etchingshape can be obtained by changing the species and composition of the gasin the course of the process. In the case of the second embodiment, itis unnecessary to etch the underlying nonconductive hydrogen barrierlayer 15.

In the step depicted in FIG. 6, the dielectric layer 4 is selectivelyetched to obtain a pattern for forming the ferroelectric capacitor. Thisprocess is carried out by the use of a photoresist mask and RIE.Subsequently, in the step depicted in FIG. 7, the nonconductive hydrogenbarrier layer 5 is deposited to a thickness of about 50 nm on the entiresurface. A plasma CVD method, in which, for example, SiH₄ and NH₃ areused as the reaction gases, is used as the deposition method. A denseSiN film having barrier properties against hydrogen is obtained bysetting the temperature during the deposition to 300° C. or higher.During this time, however, a reduction reaction takes place because ofthe hydrogen contained in the reaction gas, as described above. As aresult, the dielectric layer 4, which is patterned in the step depictedin FIG. 6, is put into a state of oxygen deficiency. In this state, theferroelectric characteristic is degraded. Subsequently, thenonconductive hydrogen barrier layer 5 is selectively etched in the stepdepicted in FIG. 8. This can be realized by the use of RIE in which CHF₃or CF₄ is used as the gas and a photoresist mask is used. Thus, theetched portions correspond to contact openings to the upper electrodelayer 6 on the dielectric layer 4 and to a part of the lower electrodelayer 3. In this step, a reduction reaction occurs in the dielectriclayer 4, resulting in an oxygen deficiency, particularly when CHF₃ isused, because hydrogen is contained in the reactive gas.

Next, in the step depicted in FIG. 9, a heat treatment is conducted inan oxygen atmosphere. The oxygen deficiency generated in the stepsdepicted in FIGS. 7-8 can be compensated by setting the temperature toabout 600° C., which is the crystallization temperature of the metaloxide PZT material in dielectric layer 4.

Thus, the ferroelectric (or high dielectric constant) characteristic isrecovered by this process. The nonconductive hydrogen barrier layer 5acts as a barrier against oxygen, as well as against hydrogen. Yet,oxygen is sufficiently supplied to the dielectric layer 4 because thenonconductive hydrogen barrier layer 5 is selectively etched on thedielectric layer 4. If the opening in accordance with the invention werenot formed on the dielectric layer 4, the characteristic would not berecoverable because oxygen would not be sufficiently supplied.

Subsequently, the upper electrode layer 6 of Pt and the secondconductive hydrogen barrier layer 7 of TiN are successively deposited onthe entire surface in the step depicted in FIG. 10. These layers aredeposited by the use of a sputtering method, mentioned above. The filmthicknesses are about 200 nm and 100 nm, respectively. Although TiN canbe deposited by a CVD method, as mentioned above, it is preferable touse a sputtering method, which causes no deterioration by reduction.

Next, these layers are selectively etched to the desired shape in thestep depicted in FIG. 11. This process is performed by the use of RIE inwhich chlorine-based gas is used with a photoresist mask. In thispattern, the openings formed in the step depicted in FIG. 8 remaincompletely covered. Thereby, the second conductive hydrogen barrierlayer 7 is patterned in the portions from which the nonconductivehydrogen barrier layer 5 was etched in this structure.

Thus, the capacitor is completely covered with either nonconductive SiNor conductive TiN in all directions, and has a structure possessingsufficient barrier properties against hydrogen.

In the case where a structure according to the third embodiment ismanufactured, as depicted in FIG. 3, the upper electrode layer 6 and thesecond conductive hydrogen barrier layer are not successively deposited.Instead, the upper electrode layer 6 is first deposited and patterned,then the second conductive hydrogen barrier layer 7 is deposited forpatterning. Thereby, the second conductive hydrogen barrier layer 7 canbe wider than the upper electrode layer 6.

Subsequently, in the step depicted in FIG. 12, the capacitor cover layer8 of NSG is deposited to a thickness of about 400 nm on the entiresurface. In such a structure, many deposition methods providingexcellent step coverage are utilizable as the deposition method, such asa normal pressure CVD method that uses TEOS (tetraethoxysilane) and doesnot cause reduction, and a plasma CVD method that uses SiH₄ and doescause reduction.

Next, in the step depicted in FIG. 13, the capacitor cover layer 8 isselectively etched to form the contact holes. In this process, RIE withCHF₃ and CF₄ is used as in the step depicted in FIG. 8. Butdeterioration due to hydrogen does not occur, even when CHF₃ is used,because of the cover of SiN and TiN.

In the step depicted in FIG. 14, wiring layer 9 is deposited on theentire surface. This layer is, for example, a laminate structure thathas Al of about 500 nm, TiN of about 100 nm, and Ti of about 50 nm, andwhich is deposited by a sputtering method. It is possible to use a CVDmethod, which causes a reduction atmosphere, for the deposition of Aland TiN because the barrier against the reduction atmosphere is inplace. In this manner, the contact resistance is reduced, and further,the yield for the memory device is improved because the step coverage ismuch better than with a sputtering method. Next, in the step depicted inFIG. 15, this structure is selectively etched. In this step, aphotoresist mask and RIE with Cl₂ are used.

A capacitor having barrier properties against hydrogen or a reductionatmosphere can be formed using the above steps. Even when a heattreatment of the capacitor is thereafter conducted in a hydrogenatmosphere at 300° C. or higher, deterioration of capacitor propertiesdoes not occur. Therefore, when a MOSFET is formed on the same basesubstrate on which the capacitor is formed according to this invention,the capacitor characteristic can be improved. In particular, thecharacteristic and the yield of the semiconductor memory using thecapacitor can be enhanced.

The ferroelectric substance mentioned for use in the embodimentsdescribed above is PZT. However, other ferroelectric substance material,such as SrBi₂Ta₂O₉, or high dielectric-constant material such as(Ba_(1−X)Sr_(X))TiO₃, may be used in this invention.

Herein, it has thus far been assumed that Pt or the laminate structureof Pt/Ti is used as the material of the upper electrode layer 6 and thelower electrode layer 3. But other materials that achieve a goodcapacitor characteristic, such as Ir, IrO₂, Ru and RuO₂, may be used andcan serve to obtain the same effect.

According to the capacitor and the method of manufacturing the same ofthis invention, a nonconductive hydrogen barrier layer covers thecapacitor except for a region on the upper electrode, while a conductivehydrogen barrier layer is formed in the region which the nonconductivehydrogen barrier film does not cover, as described above. Consequently,a capacitor with a structure having the barrier characteristic againsthydrogen or a reduction atmosphere can be obtained and, furthermore,deterioration can be suppressed in the manufacturing process. Therefore,the properties and the yield of the semiconductor memory can beimproved.

There has been described a method for fabricating ferroelectric and highdielectric-constant devices in integrated circuits that permits exposureto hydrogen and still results in ferroelectric and dielectric deviceswith good electrical properties. It should be understood that theparticular embodiments shown in the drawings and described within thisspecification are for purposes of example and should not be construed tolimit the invention, which will be described in the claims below.Further, it is evident that those skilled in the art may now makenumerous uses and modifications of the specific embodiments described,without departing from the inventive concepts. It is also evident thatthe steps recited may, in some instances, be performed in a differentorder; or equivalent structures, compositions and processes may besubstituted for the various structures, compositions and processesdescribed. Consequently, the invention is to be construed as embracingeach and every novel feature and novel combination of features presentin and/or possessed by the fabrication processes, electronic devices,and electronic device manufacturing methods described.

What is claimed is:
 1. A method of manufacturing a memory device,comprising steps of: depositing a lower electrode; depositing adielectric layer; selectively etching said lower electrode and saiddielectric layer; depositing a nonconductive hydrogen barrier layer;selectively etching said nonconductive hydrogen barrier layer;thereafter performing a ferroelectric recovery anneal in oxygen,depositing an upper electrode; and then depositing a conductive hydrogenbarrier layer; selectively etching said upper electrode and saidconductive hydrogen barrier layer; and thereafter performing a MOSFETrecovery anneal in hydrogen.
 2. A method of manufacturing a memorydevice as in claim 1, wherein: an underlying conductive hydrogen barrierlayer is formed on a base substrate before said lower electrode isformed.
 3. A method of manufacturing a memory device as in claim 2,wherein: said underlying conductive hydrogen barrier layer comprises ametal nitride.
 4. A method of manufacturing a memory device as in claim2, wherein: said metal nitride comprises one selected from the groupconsisting of TiN and AIN.
 5. A method of manufacturing a memory deviceas in claim 1, wherein: an underlying nonconductive hydrogen barrierlayer is formed on a base substrate before said lower electrode isformed.
 6. A method of manufacturing a memory device as in claim 5,wherein: said underlying nonconductive hydrogen barrier layer comprisesSiN.
 7. A method of manufacturing a memory device as in claim 5,wherein: said underlying nonconductive hydrogen barrier layer isdeposited by use of a chemical vapor deposition method.
 8. A method ofmanufacturing a memory device as in claim 1, wherein: said conductivehydrogen barrier layer comprises a metal nitride.
 9. A method ofmanufacturing a memory device as in claim 8, wherein: said metal nitridecomprises one selected from the group consisting of TiN and AIN.
 10. Amethod of manufacturing a memory device as in claim 1, wherein: a heattreatment is conducted in an oxygen atmosphere after said step ofselectively etching said nonconductive hydrogen barrier layer.
 11. Amethod of manufacturing a memory device as in claim 1, wherein: asurface is formed by said step of selectively etching said upperelectrode and said conductive hydrogen barrier layer; and furthercomprising a step of: forming a capacitor cover layer on said surface.12. A method of manufacturing a memory device as in claim 11, wherein:said step of forming a capacitor cover layer is conducted by using achemical vapor deposition method.
 13. A method of manufacturing a memorydevice as in claim 1, further comprising a step of conducting a heattreatment at a temperature of 400° C. or higher after said step ofselectively etching said nonconductive hydrogen barrier layer.
 14. Amethod of manufacturing a memory device as in claim 1, furthercomprising a step of: conducting a heat treatment in a hydrogenatmosphere after said step of depositing a conductive hydrogen barrierlayer.
 15. A method of manufacturing a memory device as in claim 14,wherein: said step of conducting a heat treatment in a hydrogenatmosphere is conducted at a temperature of 300° C. or higher.
 16. Amethod of manufacturing a memory device, comprising steps of: depositinga lower electrode; depositing a dielectric layer; selectively etchingsaid lower electrode and said dielectric layer; depositing anonconductive hydrogen barrier layer; thereafter performing aferroelectric recovery anneal in oxygen; selectively etching saidnonconductive hydrogen barrier layer; depositing an upper electrode;selectively etching said upper electrode; and then depositing aconductive hydrogen barrier layer; selectively etching said conductivehydrogen barrier layer; and thereafter performing a MOSFET recoveryanneal in hydrogen.
 17. A method of manufacturing a memory device as inclaim 16, wherein: an underlying conductive hydrogen barrier layer isformed on a base substrate before said lower electrode is formed.
 18. Amethod of manufacturing a memory device as in claim 17, wherein: saidunderlying conductive hydrogen barrier layer comprises a metal nitride.19. A method of manufacturing a memory device as in claim 18, wherein:said metal nitride comprises one selected from the group consisting ofTiN and AIN.
 20. A method of manufacturing a memory device as in claim16, wherein: an underlying nonconductive hydrogen barrier layer isformed on a base substrate before said lower electrode is formed.
 21. Amethod of manufacturing a memory device as in claim 20, wherein: saidunderlying nonconductive hydrogen barrier layer comprises SiN.
 22. Amethod of manufacturing a memory device as in claim 20, wherein: saidunderlying nonconductive hydrogen barrier layer is deposited by use of achemical vapor deposition method.
 23. A method of manufacturing a memorydevice as in claim 16, wherein: said nonconductive hydrogen barrierlayer comprises SiN.
 24. A method of manufacturing a memory device as inclaim 16, wherein: said nonconductive hydrogen barrier layer isdeposited by use of a chemical vapor deposition method.
 25. A method ofmanufacturing a memory device as in claim 16, wherein: said conductivehydrogen barrier layer comprises a metal nitride.
 26. A method ofmanufacturing a memory device as in claim 25, wherein: said metalnitride comprises one selected from the group consisting of TiN and AIN.27. A method of manufacturing a memory device as in claim 16, furthercomprising a step of conducting a heat treatment at a temperature of400° C. or higher after said step of selectively etching saidnonconductive hydrogen barrier layer.
 28. A method of manufacturing amemory device as in claim 27, wherein: said heat treatment is conductedin an oxygen atmosphere.
 29. A method of manufacturing a memory deviceas in claim 16, wherein: a surface is formed by said step of selectivelyetching said upper electrode and said conductive hydrogen barrier layer;and further comprising a step of: forming a capacitor cover layer onsaid surface.
 30. A method of manufacturing a memory device as in claim29, wherein: said step of forming a capacitor cover layer is conductedby using a chemical vapor deposition method.
 31. A method ofmanufacturing a memory device as in claim 16, further comprising a stepof: conducting a heat treatment in a hydrogen atmosphere after said stepof depositing a conductive hydrogen barrier layer.
 32. A method ofmanufacturing a memory device as in claim 31, wherein: said step ofconducting a heat treatment in a hydrogen atmosphere is conducted at atemperature of 300° C. or higher.
 33. A method of manufacturing a memorydevice as in claim 16, wherein: a heat treatment is conducted in anoxygen atmosphere after said step of selectively etching saidnonconductive hydrogen barrier layer.